Field of the Invention
The present invention relates to a substrate, a semiconductor device, and a manufacturing method of the substrate.
Description of Related Art
In semiconductor devices, performance improvement has been realized by improving a two-dimensional integration rate. However, limits on both miniaturization technology and performance improvement by miniaturization are recognized. For this reason, three-dimensional integration has been provided as one means for improving the performance. Structures such as chip-on-hoard (COB), chip-on-chip (COC), chip-to-wafer (C2W), wafer-to-wafer (W2W) and so on have been studied as such means. In the chip-on-board, a semiconductor chip is directly mounted on a wiring substrate. In the chip-on-chip, a plurality of semiconductor chips are stacked.
As a mounting method, a flip chip method, a wafer bonding method, or the like is used. A method of connecting a plurality of substrates in a vertical direction using a bump electrode, a through silicon via (TSV) and so on is generally used. For example, attempts have been made to realize semiconductor devices with higher performance by stacking a plurality of semiconductor substrates while forming connection electrodes at high density. In view of the above circumstances, a device (semiconductor memory, semiconductor imaging device, and so on) with a stacked structure having a plurality of semiconductor layers has been developed.
Measures against variation in heights of the bump electrodes have been studied in the above-described technique for connecting the plurality of substrates. For example, there is a method of pressing the bump electrodes by applying pressure during mounting. However, distortion remains inside the bump electrodes due to excessive pressing. This may cause a malfunction. Therefore, there is a method of reducing a necessary pressure by flattening a surface of the bump electrodes using a planarization technique.
In Japanese Unexamined Patent Application, First Publication No. 2009-302511, a technique is disclosed for reducing the variation in the heights of the bumps formed on a substrate. In this technique, a first bump layer filled with a metal material is formed on a substrate. A second bump layer formed of a sintered body of metal powder is formed on the first bump layer.